A reference load includes a parallel connection of a resistor load having a resistor and a transistor load having a plurality of transistors, wherein a temperature coefficient of the resistor load is positive, and a temperature coefficient of the transistor load is negative.

A power supply system for USB Power Delivery includes a current source drive circuit to control a power FET to regulate the supply of power along a power path. The current source drive circuit includes a cascode current source and a cascode protection circuit formed by a source follower and a feedback voltage divider. The source follower can be a transistor with its gate connected to a cascode node between upper- and lower-stage transistors of the cascode current source. The divider node of the voltage divider is connected to the gate of the lower-stage transistor. The current source drive circuit can operate within the gate-source voltage specifications of 30-volt DEPMOS devices, and can provide high output impedance to the gate of power FET and a current limit circuit during current limiting operation, without requiring an extra high-voltage mask during fabrication.

A front-end module comprises a low-dropout (LDO) voltage regulator, a reference current generator, and a power amplifier. The LDO voltage regulator, reference current generator, and power amplifier are integrated on a first semiconductor die.

In an example, an integrated circuit includes a junction-gate field effect transistor (JFET), a current generator, a dynamic filter, and an output transistor. The JFET has a JFET gate, a JFET source, and a JFET drain, the JFET drain adapted to be coupled to a power supply. The current generator has a current generator input and current generator outputs, the current generator input coupled to the JFET source and a first of the current generator outputs coupled to the JFET gate. The dynamic filter has a dynamic filter input and a dynamic filter output, the dynamic filter input coupled to a second of the current generator outputs. The output transistor has an output transistor gate coupled to the dynamic filter output.

An aspect of the disclosure relates to a reference voltage generator, including: a first field effect transistor (FET) including a first threshold voltage; a second FET including a second threshold voltage different than the first threshold voltage; a gate voltage generator coupled to gates of the first and second FETs; a first current source coupled in series with the first FET between first and second voltage rails; a second current source; and a first resistor coupled in series with the second current source and the second FET between the first and second voltage rails, wherein a reference voltage is generated across the first resistor.

The present invention discloses a reference circuit with temperature compensation, which is characterized in that a current output circuit is designed to receive a reference voltage from a bias voltage generation circuit, generate two reference currents with opposite temperature variation characteristics, and then merge them into a compensated current with temperature compensation. In addition, a voltage output circuit is designed to receive a reference voltage from a bias voltage generation circuit, which includes several field-effect transistors operating in saturation regions, and a precision voltage increases with threshold voltages of the field-effect transistors to compensate for the temperature variation. Resistors can be incorporated or sizes of the field effect transistors can be changed to adjust the output current, output voltage or the temperature variation characteristics.

A reference voltage circuit (1) includes a PTAT voltage generation circuit (20) that generates a voltage with a positive temperature coefficient, a CTAT voltage generation circuit (10) that generates a voltage with a negative temperature coefficient, and a temperature characteristic adjustment circuit (30) that generates a voltage for adjusting temperature characteristics. The reference voltage circuit outputs a reference voltage (VOUT) formed by calculation based on the output of the PTAT voltage generation circuit, output of the CTAT voltage generation circuit, and output of the temperature characteristic adjustment circuit.

A front-end module comprises a bias network including a current mirror, a junction temperature sensor, an n-bit analog-to-digital converter, an n-bit current source bank configured to automatically set reference current levels for one or more operating temperature regions, and a power amplifier. The bias network, junction temperature sensor, n-bit analog-to-digital converter, n-bit current source bank, and power amplifier are integrated on a first semiconductor die.

Programmable temperature regulation circuits, and methods of operating programmable temperature regulation circuits, are disclosed for providing heat to a target area on a chip. The programmable temperature regulation circuits include a heating element on the chip, and a regulation loop operatively connected to the heating element. The regulation loop includes a first diode that measures the temperature in the target area, and an operational transconductance amplifier. The operational transconductance amplifier receives a reference temperature voltage from a reference voltage, and a temperature feedback voltage from the diode, and generates an output voltage to control the provision of electrical power to the heating element.

A thermally-isolated-metal-oxide-semiconducting (TMOS) sensor has inputs coupled to first and second nodes to receive first and second bias currents, and an output coupled to a third node. A tail has a first conduction terminal coupled to the third node and a second conduction terminal coupled to a reference voltage. A control circuit applies a control signal to a control terminal of the tail transistor based upon voltages at the first and second nodes so that a common mode voltage at the first and second nodes is equal to a reference common mode voltage. A differential current integrator has a first input terminal coupled to the second node and a second input terminal coupled to the first node, and provides an output voltage indicative of an integral of a difference between a first output current at the first input terminal and a second output current at the second input terminal.