Disclosed is a voltage reference buffer circuit including a first, second, third, and fourth bias generators and a first, second, third, and fourth driving components. The first, second, third, and fourth bias generators generate bias voltages to control the first, second, third, and fourth driving components respectively. The first, second, third, and fourth driving components are coupled in sequence, wherein the first and second driving components are different types of transistors and jointly output a first reference voltage, the third and fourth driving components are different types of transistors and jointly output a second reference voltage, and the group of the first and second driving components is separated from the group of the third and fourth driving components by a resistance load.

A power supply system for USB Power Delivery includes a current source drive circuit to control a power FET to regulate the supply of power along a power path. The current source drive circuit includes a cascode current source and a cascode protection circuit formed by a source follower and a feedback voltage divider. The source follower can be a transistor with its gate connected to a cascode node between upper- and lower-stage transistors of the cascode current source. The divider node of the voltage divider is connected to the gate of the lower-stage transistor. The current source drive circuit can operate within the gate-source voltage specifications of 30-volt DEPMOS devices, and can provide high output impedance to the gate of power FET and a current limit circuit during current limiting operation, without requiring an extra high-voltage mask during fabrication.

Disclosed is a voltage reference buffer circuit including a first, second, third, and fourth bias generators and a first, second, third, and fourth driving components. The first, second, third, and fourth bias generators generate bias voltages to control the first, second, third, and fourth driving components respectively. The first, second, third, and fourth driving components are coupled in sequence, wherein the first and second driving components are different types of transistors and jointly output a first reference voltage, the third and fourth driving components are different types of transistors and jointly output a second reference voltage, and the group of the first and second driving components is separated from the group of the third and fourth driving components by a resistance load.

Systems, methods, circuits, and apparatus including computer-readable mediums for managing bit line voltage generating circuits in memory devices are provided. An example bit line voltage generating circuit is configured to provide a stable clamping voltage to at least one bit line connecting memory cells in the memory device. The bit line voltage generating circuit includes an operational amplifier configured to receive a reference voltage, a feedback voltage, and a compensation current and output an output voltage, and an output transistor configured to provide a terminal voltage as the feedback voltage and the output voltage as a target voltage that is associated with the clamping voltage. The operational amplifier is configured to be unbalanced such that the terminal voltage is smaller than the reference voltage, and the compensation current is configured to compensate the operational amplifier such that the clamping voltage is substantially constant and independent from PVT (Process-Voltage-Temperature) effect.

A voltage reference circuit comprises: a first transistor; a second transistor, wherein the first transistor and the second transistor are arranged in a stacked connection between a terminal connected to ground and a terminal connected to a supply voltage, wherein a reference voltage is output at an output node between the first transistor and the second transistor; and a regulating transistor, wherein the regulating transistor is connected between the supply voltage and the first transistor in a stacked connection with the second transistor, wherein a bulk terminal of the regulating transistor is connected to the output node for compensating changes in the reference voltage at the output node to maintain a stable reference voltage level.

A voltage detector has a diode ladder with one or more diodes connected in series between a battery voltage input and an upper measuring node. A measuring diode is connected between the upper measuring node and a lower measuring node. A resistor and a power-down switch are connected in series between the lower measuring node and a ground. An analog input to an Analog-to-Digital Converter (ADC) is connected by a switch to the upper measuring node to generate an upper digital value. Then the switch connects the analog input to the lower measuring node to generate a lower digital value. The difference between the upper and lower digital values is the diode voltage drop across the measuring diode and is multiplied by a number of diodes in the diode ladder and added to the upper digital value to generate a battery voltage measurement.

Disclosed herein is a regulator for a non-volatile memory. The regulator comprises a high voltage supply terminal, a low voltage supply terminal, an output terminal, a ground terminal and an internal node. The regulator further comprises an input amplifier inserted between the low voltage supply terminal and the ground terminal and outputting a first output voltage at a first intermediate output node according to a reference voltage and a feedback voltage provided at its negative and positive input terminals, respectively; a mirror circuit forming two current paths between the internal node and the ground terminal and between the internal node and a second intermediate output node respectively; and a cascode block coupled between the high voltage supply terminal and the internal node and operating in response to a voltage at the second intermediate output node of the regulator where the two current path is formed by the mirror circuit.

A high voltage logic circuit for high voltage system application comprises a first device layer formed from a first semiconductor material and comprises a low voltage logic circuit; and a second device layer formed from a second different semiconductor material and comprising one or more components of an additional circuit for generating a high voltage logic output from a low voltage logic input from the low voltage logic circuit; wherein the first and second device layers are integrally formed. Also, a logic circuit comprising: a low voltage logic input; a high supply voltage input; a circuit ground voltage input; a high voltage output; a first tail device made from a first semiconductor material; and a second tail device made from a second different semiconductor material; wherein the first and second tail devices are coupled, in series, between the high voltage output and the circuit ground voltage input; and wherein respective gates of the first and second tail devices are coupled, in parallel, to the low voltage logic input.

Disclosed herein is a regulator for a non-volatile memory. The regulator comprises a high voltage supply terminal, a low voltage supply terminal, an output terminal, a ground terminal and an internal node. The regulator further comprises an input amplifier inserted between the low voltage supply terminal and the ground terminal and outputting a first output voltage at a first intermediate output node according to a reference voltage and a feedback voltage provided at its negative and positive input terminals, respectively; a mirror circuit forming two current paths between the internal node and the ground terminal and between the internal node and a second intermediate output node respectively; and a cascode block coupled between the high voltage supply terminal and the internal node and operating in response to a voltage at the second intermediate output node of the regulator where the two current path is formed by the mirror circuit.

An electronic circuit is disclosed. The electronic circuit includes a reference voltage generator, which includes a first candidate circuit configured to generate a first candidate reference voltage, a second candidate circuit configured to generate a second candidate reference voltage, and a selector circuit configured to select one of the first and second candidate reference voltages. The reference voltage generator also includes a third circuit configured to generate a power supply voltage based on the selected candidate reference voltage.