An integrated circuit device having insulated gate field effect transistors (IGFETs) having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure has been disclosed. The integrated circuit device may include a temperature sensor circuit and core circuitry. The temperature senor circuit may include at least one portion formed in a region other than the region that the IGFETs are formed as well as at least another portion formed in the region that the IGFETs having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure are formed. By forming a portion of the temperature sensor circuit in regions below the IGFETs, an older process technology may be used and device size may be decreased and cost may be reduced.

An active common mode filter is configured to be positioned between a power supply and a switching converter-device/load for reducing common mode noise. The active common mode filter includes an active capacitor that has a sensing stage including one or more sensing capacitors, an amplifying stage including a common collector amplifier for mitigating an input voltage divider effect coupled to a common emitter amplifier for providing high gain, and an injection stage including one or more injection capacitors. Depending on the required attenuation in different applications, a multistage active common mode filter may be formed with a necessary number of stages, each stage including an active capacitor and an inductor.

Provided is a reference voltage circuit configured to supply a reference voltage in which a variation in voltage with respect to a variation in power supply voltage is suppressed. The reference voltage circuit includes a reference voltage generation circuit which includes an output line for supplying a generated reference voltage to an output terminal; and an output control circuit which includes an output transistor and a stabilization transistor, and is configured to control the supply of the reference voltage to the output terminal, the output transistor containing a gate to which a control voltage is to be provided, the stabilization transistor containing a gate to be connected to a source of the output transistor, and a source to be connected to a drain of the output transistor, and having a gate-source voltage that is equal to or more than a dram-source voltage in a saturation region of the output transistor.

Disclosed is a bandgap reference circuit, which includes a first current generator that generates a first current proportional to a temperature, a second current generator that outputs a second current obtained by mirroring the first current to a first node at which a reference voltage is formed, a first resistor that is connected with the first node and is supplied with the second current, and a first bipolar junction transistor (BJT) that includes an emitter node connected with the first resistor, a base node supplied with a first power, and a collector node supplied with a second power different from the first power.

The device includes at least the following components: a heating resistor intended for heating a component to be regenerated; a current source; a thermistor connected to the current source and thermally coupled to the heating resistor, the thermistor, through which the current flows, having a voltage Vtemp across its terminals, which voltage reflects the temperature of the heating resistor; an error amplifier, which amplifies the difference between the voltage Vset and the voltage Vtemp and delivers a voltage Vctrl that corresponds to the amplified difference; a switch, which switches the current flowing through the heating resistor; an oscillator, which delivers a voltage Vosc formed with a modulated duty cycle, the duty cycle of the pulses of the voltage Vosc being dependent on the voltage Vctrl, the pulses controlling the opening of the switch.

Circuits for generating a PTAT voltage as a base-emitter voltage difference between a pair of bipolar transistors. The circuits may form unit cells in a cascading voltage reference circuit that increases the PTAT voltage with each subsequent stage. The bipolar transistors are controlled using a biasing arrangement that includes an MOS transistor connected to a current mirror that provides the base current for the bipolar transistors. A voltage reference is formed by combining a PTAT voltage and a CTAT voltage at the last stage. The voltage reference may be obtained from the voltage at an emitter of one of the bipolar transistors in the last stage.

An integrated circuit device having insulated gate field effect transistors (IGFETs) having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure has been disclosed. The integrated circuit device may include a temperature sensor circuit and core circuitry. The temperature senor circuit may include at least one portion formed in a region other than the region that the IGFETs are formed as well as at least another portion formed in the region that the IGFETs having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure are formed. By forming a portion of the temperature sensor circuit in regions below the IGFETs, an older process technology may be used and device size may be decreased and cost may be reduced.

An integrated circuit device having insulated gate field effect transistors (IGFETs) having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure has been disclosed. The integrated circuit device may include a temperature sensor circuit and core circuitry. The temperature senor circuit may include at least one portion formed in a region other than the region that the IGFETs are formed as well as at least another portion formed in the region that the IGFETs having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure are formed. By forming a portion of the temperature sensor circuit in regions below the IGFETs, an older process technology may be used and device size may be decreased and cost may be reduced.

A voltage reference circuit including a resistive track having a first force contact and a second force contact. The first and second force contacts configured to pass a current through the resistive track. A first sense contact, a second sense contact and a third sense contact are arranged at different positions along the resistive track between the first and second force contacts and the sense contacts are arranged to define a first resistor and a second resistor. A first component arrangement includes a P-N junction which has a temperature dependent voltage bias; a second component arrangement. One or both of the first component arrangement and the second component arrangement provide for a counter-bias voltage. The counter bias voltage counters the temperature dependent voltage bias of the P-N junction such that the voltage reference circuit provides a constant output reference voltage.

An example current mirror arrangement includes a current mirror circuit, configured to receive an input current signal at an input transistor Q1 and output a mirrored signal at an output transistor Q2. The arrangement further includes a semi-cascoding circuit that includes transistors Q3, Q4, and a two-terminal passive network. The transistor Q3 is coupled to, and forms a cascode with, the output transistor Q2. The transistor Q4 is coupled to the transistor Q3. The base/gate of the transistor Q3 is coupled to a bias voltage Vref, and the base/gate of the transistor Q4 is coupled to a bias voltage Vref1 via the two-terminal passive network. Nonlinearity of the output current from such a current mirror arrangement may be reduced by selecting appropriate impedance of the two-terminal passive network and selecting appropriate bias voltages Vref and Vref1.